VHDL Synthesis Interoperability Working Group

Scope:
To develop a standard syntax and semantics for VHDL RTL synthesis. This standard shall define the subset of IEEE 1076 (VHDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standards IEEE 1076, 1164, and 1076.3.

Purpose:
The purpose of this standard is to define a syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use the current IEEE 1076 standard. This will allow users of synthesis tools to produce well defined designs whose functional characteristics are independent of an particular synthesis implementation by making their designs compliant with this developed standard.

For voting privileges under DASC (1076.6 is sponsored by the DASC), you will need to be a member of DASC (click here to enroll as a DASC member). Even if you are not interested in voting privileges, you are encouraged to become a DASC member as it helps in supporting the DASC expenses which includes running the 1076.6 working group meetings

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