Articles and Insights

Portable Stimulus: The Making of a Standard

Gabe Moretti

by Gabe Moretti
August 15, 2017

The Accellera-sponsored DVCon U.S. 2017 covered, among many other topics, the work on the Portable Stimulus proposed standard. I took the opportunity to interview the leaders of the Accellera Working Group (WG) that is developing it: Faris Khundakjie, leading technologist at Intel and Chair of the WG and Tom Fitzpatrick, Verification Technologist, Design Verification & Test Division at Mentor Graphics, the WG Vice Chair.

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DVCon India 2016: A Success in the Making

Gabe Moretti

by Gabe Moretti
August 23, 2016

The third edition of DVCon India will be held September 15 and 16 at the Leela Palace hotel in Bangalore. Accellera System Initiative, the conference sponsor, is continuing to enlarge its community of professionals by bringing to India a unique opportunity for engineers at all levels to learn, share, and network. Traveling costs are so high in comparison to the registration and hotel costs to make it impractical for Indian engineers to travel to San Jose to attend the original DVCon every year. By sponsoring local DVCon conferences in India and Europe so far, and in China beginning next year, Accellera demonstrates its interest in serving design and verification professionals worldwide.

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DVCon: Building a Community Through Quality Conferences

Gabe Moretti

by Gabe Moretti
April 26, 2016

Accellera System Initiative has held an annual DVCon conference since its inception. Although Accellera is a consortium of companies, its focus is on practicing engineers. One of the ways it creates an environment for professional growth is through its DVCon conferences. Unlike most other conferences covering the EDA industry, DVCon is focused on practicing design and verification engineers. The mission of DVCon is to facilitate networking and professional growth of engineers.

Two years ago, Accellera expanded its services by starting DVCon India and DVCon Europe, making DVCon the only EDA conference held in all three continents. The major reason for this growth is the quality of papers presented at each event, both those delivered in technical sessions and those shown as poster presentations.

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DVCon U.S. 2016 Tackles Pressing Design and Verification Issues

Gabe Moretti

by Gabe Moretti
February 9, 2016

Within the EDA industry, the Design & Verification Conference and Exhibition (DVCon) has created one of the most successful communities of the 21st century. Started as a conference dealing with two design languages, Verilog and VHDL, DVCon has grown to cover all aspects of design and verification. Beginning as a conference based in Silicon Valley, the conference is now held on three continents: America, Asia and Europe. Both DVCon Europe and DVCon India have shown significant growth, and plans are well on their way to offer a DVCon in China as well.

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DVCon Europe to Energize Munich in November

Gabe Moretti

by Gabe Moretti
October 27, 2015

The second DVCon Europe conference will be held in Munich, Germany on November 11–12.  The conference is sponsored by Accellera Systems Initiative and follows the very successful first edition held last fall.  Martin Barnasconi, General Chair of this year’s conference, remarked on the success of the first conference: “With more than 250 attendees in 2014, full tutorial rooms, a good variety of technical presentations and a nicely crowded exhibition floor, we can conclude that DVCon Europe fulfils a clear need: an industry-oriented conference, focusing on design and verification of electronic systems and integrated circuits.”  

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DVCon India was a Great Success

Gabe Moretti

by Gabe Moretti
October 5, 2015

Although only its second yearly event, the success of the Design and Verification Conference and Exhibition India (DVCon India), sponsored by Accellera Systems Initiative, underscored the key role played by Accellera in supporting the electronics industry, and EDA in particular, worldwide.

Starting a new conference at the time when companies are cutting back their travel budget is a risky proposition, but Accellera proved that an event rich in technical information and the opportunity to network with peers is still considered a valuable corporate investment.

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DVCon India: A Growing Event

Gabe MorettiBy Gabe Moretti
September 2, 2015

Launched with great success last year, DVCon India is back this year with an expanded program.  This year the conference will be held in Bangalore on September 10 and 11 at the Leela Palace.  Sponsored by Accellera Systems Initiative, the conference will provide opportunities for professional growth, networking, and familiarization with the standardization work that goes on in Accellera.  The success of the first DVCon India has resulted in moving the conference to a larger venue, increasing both the number of technical sessions and tutorials as well as increasing the exhibit space.  The exhibit booths will be open both days of the conference in order to offer flexibility to attendees as they plan their daily schedules.

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Accellera at DAC and Beyond

Gabe MorettiBy Gabe Moretti
June 30, 2015

Accellera has a strong tradition at DAC presenting its Tuesday morning breakfast.  This year was not an exception.  The food was good and abundant, offering a variety of choices for both vegetarians and meat lovers alike.  The program consisted of the presentation of the Leadership Award and a panel discussion on “Design and Verification Standards in the Era of IoT.”

The Leadership Award

The award recognizes the vision, leadership, and contribution to standards development, governance and promotional activities of the organization.  The recipient of this year’s award is Dr. Bill Read.  Dr. Read has been a member of Accellera’s Board of Directors since 1998. He currently serves on the SRC/GRC Executive Technical Advisory Board. Dr. Read received his BSE, MSE and PhD degrees in Electrical Engineering from the University of Texas at Austin.

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Accellera’s UVM in SystemC Standardization: Going Universal for ESL

by Adam Sherer, Accellera Promotions Committee Chair
May 14, 2015

Reusable, modular, and scalable testbenches based on the Accellera Universal Verification Methodology (UVM) standard are used throughout the electronics industry. Thousands of engineers have used phasing, factory, configuration, reporting, and other features of the SystemVerilog-based reference implementation class library supplied by Accellera to build UVM verification components (UVC). Since these UVCs include automated stimulus generation, independent results generation, and coverage collection, many project teams are now able to implement coverage-driven verification (CDV) methodologies. Altogether, UVM is a great success bringing both reuse and improved overall verification efficiency primarily for RTL IP design.

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DVCon United States Highlights

Gabe MorettiBy Gabe Moretti
March 25, 2015

The first "DVCon United States" was a success. It was the 27th Conference of the series and the first one with this name to separate it from the newer DVCon Europe and DVCon India, which following their successful first events last year, will be held again this year.

Overall attendance, including exhibit-only and technical conference attendees, was 932. If we count, as DAC does, exhibitors personnel then the total number of attendees is 1213. The conference attracted 36 exhibitors, including 10 exhibiting for the first time and 6 of them headquartered outside of the US. The technical presentations were very well attended, almost always with standing room only, thus averaging around 175 attendees per session. One cannot fit more in the conference rooms than the DoubleTree has space for. The other thing I observed was that there was almost no attendee traffic during the presentations. People took a seat and stayed for the entire presentation. Almost no one came in, listened for a few minutes and then left. In my experience this is not typical and points out that the goal of DVCon, to present topics of contemporary importance, was met.

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DVCon 2015: Not to Be Missed

Gabe MorettiBy Gabe Moretti
February 23, 2015

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera. That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years. Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.

The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages. This year's conference is the 27th and offers an expanded technical program. In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year. Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

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Whitepaper: Advancing the SystemC Analog/Mixed-Signal (AMS) Extensions —Introducing Dynamic Timed Data Flow

By Martin Barnasconi, NXP Semiconductors and AMS Working Group Chair; Karsten Einwich, Fraunhofer IIS/EAS Dresden; Christoph Grimm, Vienna University of Technology; Torsten Maehne, Université Pierre et Marie Curie; and Alain Vachoux, École Polytechnique Fédérale de Lausanne

September 2011

To comply with demanding requirements and use cases (e.g., in automotive applications), new execution semantics and language constructs are being defined to facilitate a more reactive and dynamic behavior of the Timed Data Flow (TDF) model of computation as defined in the current SystemC AMS 1.0 standard. The proposed Dynamic TDF introduces fully complementary elements to enable a tighter time-accurate interaction between the AMS signal processing and control domain while keeping the modeling and communication abstract and efficient. The features of Dynamic TDF are presented in this paper by means of a typical example application from the automotive domain.

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Whitepaper: SystemC AMS Extensions—Solving the Need for Speed

By Martin Barnasconi, AMS Working Group Chair
May 2010

Similar to Transaction-level Modeling (TLM), the SystemC AMS extensions introduce smart methods to abstract time and uses known techniques to abstract signal properties. However, analog behavior is continuous in time and continuous in value, captured in an equation system and often seen as difficult to abstract. Any abstraction method applied would result in a less accurate description of the analog behavior. This is not necessarily a problem, as long as the abstracted behavior does not impact the essential characteristics or functionality of the AMS system for the intended application. So, when applying these abstraction methods in a smart manner, a major improvement in simulation speed is obtained, enabling totally new AMS analysis and verification methods through simulation, which have never been exercised before.

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Viewpoint: The Next IC Design Methodology Transition Is Long Overdue

By Michael Meredith and Steve Svoboda, February 2010

Given that the RTL design abstraction has been in use for more than 15 years, it is no longer possible to consider it the leading-edge design approach that is required to bring us new, exciting consumer and industrial electronic products. Fortunately the move to the next level of abstraction using high-level synthesis in SystemC is well underway, and is demonstrating that it can deliver the required productivity.

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Viewpoint: Analog/Mixed-Signal (AMS) extensions for SystemC

By Martin Barnasconi, AMS Working Group Chair
February 2009

The AMS draft 1 standard focuses on the system-level and architecture modeling aspects of designing and verifying complex AMS systems. By having AMS extensions for SystemC, users can build an executable description of the AMS system in a C++ based manner, enabling seamless integration with HW/SW architectures in SystemC and functional models or software developed in C and C++. As such, the AMS extensions should not be considered as a replacement of existing hardware description languages, but should be seen as a valuable addition to ESL design methodologies.

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An Insider's View on the Making of the New TLM-2.0 Standard

By Bart Vanthournout, TLM Working Group Chair
June 2008

Why is TLM-2.0 so important? TLM-2.0 standard interfaces for SystemC provides an essential framework needed for model exchange within companies and across the IP supply chain for architecture analysis, software development and performance analysis, and hardware verification. It explicitly addresses virtual prototyping in which SystemC models can easily be exchanged and arranged within a system. By providing a strong modeling foundation for virtual prototyping, the standard enables optimal reuse of models and modeling effort across different use cases.

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