Working Groups

The mission of Accellera Systems Initiative is to deliver standards that lower the cost of designing commercial IC and EDA products and embedded system solutions, as well as increase the productivity of designers worldwide. The Technical Committee is where this mission is realized, and through its dedicated work, EDA and IP standard are developed that enable and promote technology innovation.

The Board of Directors of Accellera Systems Initiative established the Technical Committee (TC) to develop, update and extend hardware design language (HDL) and intellectual property (IP) standards. The TC is comprised of working groups that focus on the various standards under development, and report to the TC Chair. In addition, Accellera supports activities of certain IEEE working groups and cooperates with other standards groups within the EDA industry.

Membership at the Corporate or Associate level is required to join a Working Group or have a vote on specifications and standards. Learn more about the different levels of membership.

Active Working Groups

Working Group Chair
Clock Domain Crossing Iredamola Olopade, Intel
Federated Simulation Standard (FSS) Martin Barnasconi, NXP
Functional Safety Alessandra Nardi, Synopsys
IP-XACT Erwin de Kock, NXP
Multi-Language (ML) Warren Stapleton, AMD
Portable Stimulus Matthew Ballance, AMD
SystemC Analog/Mixed-Signal (AMS) Martin Barnasconi, NXP
SystemC Configuration, Control and Inspection (CCI) Lukas Jünger, MachineWare
SystemC Language Laurent Maillet-Contoz, ST Microelectronics
SystemC Common Practices Mark Burton, Qualcomm
SystemC Datatypes Frederic Doucet, Qualcomm
SystemC Transaction-level Modeling (TLM) Bart Vanthournout, Synopsys
SystemC Synthesis Frederic Doucet, Qualcomm
SystemC Verification Stephan Gerth, Bosch
SystemVerilog-AMS (Analog Mixed-Signal) Peter Grove, Renesas
SystemVerilog-MSI (Mixed-Signal Interface Types) Tom Fitzpatrick, Siemens DISW
Universal Verification Methodology (UVM) Mark Strickland, Marvell
UVM-MS (Mixed-Signal extensions for UVM) Tom Fitzpatrick, Siemens DISW

Dormant Working Groups