Accellera Forms SystemVerilog Mixed-Signal Interface Types Working Group

New Working Group to Focus on Language Extensions, Including Bidirectional Connections

Elk Grove, Calif., February 7, 2024 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the SystemVerilog Mixed-Signal Interface Types (SystemVerilog MSI) Working Group (WG).

The scope of the new working group is to document a SystemVerilog-compatible language extension to permit interconnect, conversion, and resolution among dissimilar net types in SystemVerilog, including bidirectional connections.

“Accellera continues to look for opportunities to develop standards that will improve design and verification productivity for electronic product development,” stated Lu Dai, Chair of Accellera. “The SystemVerilog MSI Standard will create efficiencies for engineers using the upcoming Verilog-AMS and UVM-MS (formerly UVM-AMS) standards by making it easier to connect analog and mixed-signal models to SystemVerilog designs.”

The new working group will be chaired by Tom Fitzpatrick, who is also Chair of the UVM-MS and IEEE Std 1800 working groups, and co-chaired by Peter Grove, who is also the SystemVerilog-AMS Working Group Chair and UVM-MS Co-chair.

“Our goal is to release this new standard as an addendum to IEEE Std. 1800™-2023,” stated Fitzpatrick. “Vendors will be able to rely on this new standard to implement the functionality quickly to provide users a reliable platform with which to model and simulate complex mixed-signal design and verification environments.”

“We expect this new functionality to enable the SystemVerilog-AMS standard to bypass some limitations that were present in Verilog-AMS,” added Grove.


The Accellera UVM-MS and SystemVerilog-AMS Working Groups have illustrated that there is a fundamental need for support of bidirectional net connections between logic/UDN (User-Defined Nets) and analog/electrical/real signals as an integral part of IEEE 1800.

Past efforts to add similar functionality outside of IEEE 1800, such as Verilog-AMS connect modules, have proven unable to address the complexity and usability requirements that have arisen in typical System-on-Chip designs. Over time various limitations have had to be addressed by EDA vendors.

The SystemVerilog MSI Working Group is tasked with resolving these issues.

The first meeting of the new working group is planned for mid-March. For more information on the SystemVerilog MSI Working group, visit the working group page. If you are not already an Accellera member and are interested in joining to participate in the working group and the ongoing development of the standard, visit here.

About Accellera Systems Initiative

Accellera Systems Initiative is an independent, not-for-profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit Find out more about membership. Follow @accellera on Twitter and LinkedIn or to comment, please use #accellera. Accellera Global Sponsors are Cadence, Siemens EDA, and Synopsys.


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