Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release

New standard provides MS extensions for UVM, improving verification

Elk Grove, Calif., February 4, 2025 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Board of Directors has approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard for release. The new standard is available for immediate download fee free.

The UVM-MS 1.0 standard is a comprehensive and unified analog/mixed-signal (AMS) verification methodology based on the UVM IEEE Std. 1800.2™. This standard significantly enhances the verification of AMS and digital/mixed-signal (DMS) integrated circuits and systems. It defines a robust framework that facilitates the creation of AMS verification components and testbenches by extending digital-centric UVM classes and enabling interaction between class-based and structural environments.

“I’d like to congratulate the members of the UVM-MS Working Group for their dedication and hard work in delivering this much-anticipated standard that will significantly enhance the verification of AMS products and applications,” stated Lu Dai, Chair of Accellera. “The strong industry interest in this standard underscores its importance. As an organization devoted to improving design and verification productivity for both users and vendors, we eagerly anticipate its positive impact on the industry.”

UVM-MS 1.0 introduces the concept of the MS Bridge, a SystemVerilog module that connects UVM agents to mixed-signal DUTs. This bridge includes an MS Proxy class, which provides an API to control the bridge core. The MS Bridge Core handles datatype conversions and signal manipulations, ensuring accurate modeling of analog behaviors. This comprehensive approach standardizes methods for driving and monitoring mixed-signal nets within UVM, significantly enhancing the productivity and quality of verification processes for AMS and DMS designs.

“The release of UVM-MS 1.0 is a game changer for the verification of AMS designs,” said Tom Fitzpatrick, Chair of the UVM-MS Working Group. “This unified approach will help to make the verification of components and subsystems much more efficient and enable the development of reusable UVM-MS verification components, similar to Verification IP available today in UVM for digital verification. I’m deeply grateful for the hard work and collaboration of our working group members whose expertise made this achievement possible.”

The long-term goal for the UVM-MS standard is to enhance its global reach and recognition by transitioning it to the IEEE Design Automation Standards Committee (DASC) for formal standardization. This collaboration will leverage the IEEE’s extensive global network and perspective, ensuring ongoing maintenance, greater adoption, and sustained development of the standard worldwide.

For more information about the UVM-MS standard, visit the UVM-MS Working Group page.

About Accellera
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter and LinkedIn or to comment, please use #accellera. Accellera Global Sponsors are: Cadence, Siemens EDA, and Synopsys.

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